`timescale  1ns / 1ps

module tb_top;

parameter PERIOD  = 10;

reg   w_sysclk                             = 0 ;
reg   w_sysrst                             = 1 ;
reg   [1:0]  mode                          = 2'b11 ;

always #(PERIOD/2)  w_sysclk=~w_sysclk;

initial
begin
    #(PERIOD*5)  w_sysrst=0;
end

wire signed [31:0]  o_z             ;     
wire signed [31:0]  o_x             ;    
wire signed [31:0]  o_y             ; 

reg  signed [31:0]  i_z             ;     
reg  signed [31:0]  i_x             ;    
reg  signed [31:0]  i_y             ;    
reg                 r_valid         ;  

wire                w_ready         ;      
wire signed [31:0]  w_sin           ;    
wire signed [31:0]  w_cos           ;    
wire                w_result_valid  ;

Cordic_Module Cordic_Module_u0(
    .i_clk           (w_sysclk      ),
    .i_rst           (w_sysrst      ),

    .i_z             (i_z           ),
    .i_x             (i_x           ),
    .i_y             (i_y           ),
    .i_valid         (r_valid       ),
    .mode            (mode          ),   
    .o_ready         (w_ready       ),

    .o_z             (o_z           ),
    .o_x             (o_x           ),
    .o_y             (o_y           ),
    .o_result_valid  (w_result_valid)  
);

always@(posedge w_sysclk,posedge w_sysrst)
begin
    if(w_sysrst) begin
        i_z <= 'd2400;
        i_x <= 'd1068;
        i_y <= 'd0;
        r_valid <= 'd0;
    end else if(r_valid & w_ready) begin
        i_z <= i_z;
        r_valid <= 'd0;
    end else if(w_ready) begin 
        //圆周旋转
        // i_z <= 300000;
        // i_x <= 1023;      
        // i_y <= 0;                
        // r_valid <= 'd1;        

        //圆周向量
        // i_z <= 0;
        // i_x <= 1023;      
        // i_y <= 1023;                
        // r_valid <= 'd1;

        //线性旋转
        // i_z <= i_z < 32'd15000 ? i_z + 32'd500 : 32'd15000;
        // i_x <= 1023;      
        // i_y <= 0;                
        // r_valid <= 'd1;

        //线性向量
        i_z <= 0;
        i_x <= i_x < 32'd10023 ? i_x + 32'd500 : 32'd10023;      
        i_y <= 2024;                
        r_valid <= 'd1;

    end else begin
        i_z <= i_z;
        r_valid <= 'd0;
    end
end





endmodule
